Current demands for high density and performance associated with ultra large scale integration require submicron features, increased transistor and circuit speeds, and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring. Careful process monitoring typically includes frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
One important process requiring careful inspection is photolithography, wherein masks are used to transfer circuitry patterns to semiconductor wafers. Typically, a series of such masks are employed in a preset sequence. Each photolithographic mask includes an intricate set of geometric patterns corresponding to the circuit components to be integrated onto the wafer. Each mask in the series is used to transfer its corresponding pattern onto a photosensitive layer (e.g., a photoresist layer), which has been previously coated on a layer, such as a polysilicon or metal layer formed on the silicon wafer. The transfer of the mask pattern onto the photoresist layer is performed by an optical exposure tool such as a scanner or a stepper, which directs light or other radiation through the mask to expose the photoresist. The photoresist is thereafter developed to form a photoresist mask, and the underlying polysilicon or metal layer is selectively etched in accordance with the mask to form features such as lines or gates.
Fabrication of the mask follows a set of predetermined design rules set by processing and design limitations. These design rules define the space tolerance between devices and interconnecting lines and the width of the lines themselves, to ensure that the devices or lines do not overlap or interact with one another in undesirable ways. Design rules set limits on critical dimension (“CD”), which may be defined as any linewidth of interest in a device containing a number of different linewidths. The CD for most features in ultra large scale integration applications is on the order of a fraction of a micron, however, it generally depends on the specific feature.
As design rules shrink and process windows (e.g., the margins for error in processing) become smaller, inspection and measurement of surface feature CD's, as well as their cross-sectional shape (“profile”) are becoming increasingly important. Deviations of a feature's CD and profile from design dimensions may adversely affect the performance of the finished semiconductor device. Furthermore, the measurement of a feature's CD and profile may indicate processing problems, such as stepper defocusing or photoresist loss due to over-exposure.
Current CD inspection and measurement techniques, however, have various different drawbacks. Accordingly, what is needed in the art is a CD inspection and measurement technique that does not experience the drawbacks of those that currently exist.